1. Field of the Invention
The present invention relates to a memory device and, more particularly, to a nonvolatile memory device and a method of making thereof.
2. Background of the Related Art
There are two factors that determine an effective size of a memory cell, which determines a packing density of a nonvolatile memory device, such as an electrically erasable programmable read only memory (EEPROM) or a flash EEPROM. One of the two factors is the cell size and the other is the construction of the cell array. A memory cell having a minimum cell construction is a simple stacked-gate structure.
The applications of nonvolatile memory devices, such as EEPROMs and flash EEPROMs, are expanding. However, the cost-per-bit of a memory is expensive, and it is difficult to use nonvolatile semiconductor memories, such as EEPROMS and flash EEPROMS, as mass storage media. Moreover, chips with low power consumption are preferred for portable applications. Accordingly, much development and research has been directed to methods for diminishing the cost-per-bit.
A packing density of a conventional nonvolatile memory device depends on the number of memory cells therein. For multi bit cells, a data of one bit or more is stored in a memory cell, and it is possible to increase the packing density for storing data in an identical area of a chip without decrease of the size of a memory cell. In order to obtain the aforementioned multi bit cell, more than 2 threshold voltage levels should be programmed for each memory cell. For example, to store a data of 2 bits in a cell, each cell should be programmed to have four threshold voltage levels (2.sup.2 =4). The four threshold voltage levels represent 00, 01, 10, and 11 in a logic state. In such a multi level program, each threshold voltage level has statistical distribution of about 5 V, which is one of the significant problems.
In one of the methods for reducing the voltage distribution, a programming operation is performed by repeating programming and verifying alternately. A series of voltage pulses are applied to cells to program nonvolatile memory cells in desired threshold voltage levels. Then, a reading operation is performed between voltage pulses to verify whether or not the cells have reached the desires threshold voltage levels. During each verification, if a verified threshold voltage level value reaches a threshold voltage level value, the programming operation is halted.
However, it is difficult to reduce the error distribution of the threshold voltage levels by a finite program voltage pulse width in the aforementioned method. Further, since algorithm circuits for repeating programming and verifying alternately are needed, the periphery circuitry area of a chip is increased and a period for programming is lengthened.
FIG. 1A is a cross-sectional view of a general nonvolatile memory device having a simple stacked-gate structure, and FIG. 1B is a circuit equivalent of a general nonvolatile memory cell. A floating gate 3 is formed on a tunneling oxide film 2, which is formed on a p-type semiconductor substrate 1. On the floating gate 3, a dielectric film 4 is formed, upon which a control gate 5 is formed. N-type source drain regions 6a and 6b are formed beneath a surface of a semiconductor substrate 1 at both sides of the floating gas 3.
In such a nonvolatile memory device, an effective cell size is small, and a coupling constant of a control gate 5 is small. The smaller the effective cell size, the lower the coupling constant. Accordingly, in order to prevent the decrease of the coupling constant, a dielectric film 4 made of oxide nitride oxide (ONO) is positioned between the floating gate 3 and the control gate 5. A complex process with an annealing step at a high temperature is required to form the dielectric layer 4 of ONO.
As shown in FIG. 1B, each nonvolatile memory cell includes a floating gate 3, a control gate 5 for adjusting charges provided for the floating gate 3, a floating gate 3, a source 6a, a drain 6b, and a channel region 7 formed between the source and drain 6a and 6b. When a high program voltage is applied to the control gate 5 and the drain 6b, the current flows between the drain 6b and the source 6a. If the current is about the same as the reference current or smaller, a programming completion signal is generated.
FIG. 2A is a circuit diagram of an array of memory cells of a nonvolatile memory device. A plurality of metal bit lines 9 are formed to be spaced apart from one another by a predetermined distance in a column direction. A plurality of word lines 10 are formed at right angle to the metal bit lines 9. A common source line 11 per two word lines 10 is formed in the same direction as the word lines 10.
The drains 6b shown in FIG. 1B are connected to the metal bit lines 9 and the sources 6a are connected to the common source lines 11. Since one metal contact hole 8 per two cells is required, an effective size of memory cells becomes very big. Although an array of a general nonvolatile memory device having a simple stacked-gate structure has a minimum cell size, the actual effective size is limited by the pitch of the metal contact holes 8.
FIG. 2B illustrates an array of memory cells having a split-channel structure with selection gates 12. In this case, because the programming operation is performed by hot electron injection, the problems of program disturb and over-erase can be prevented. A nonvolatile memory device shown in FIG. 2B includes a plurality of word lines 10 formed on a semiconductor substrate (not shown) to be spaced apart from one another by a predetermined distance, a plurality of bit lines 13 formed at right angle to the word lines 10 to form a plurality of square areas, and a plurality of nonvolatile memory cells, each disposed within the square areas.
Each nonvolatile memory cell shown in FIG. 2B includes a floating gate 3 shown in FIG. 4, a control gate 5 for adjusting an amount of charge provided for the floating gate 3 for programming, and an electric field effect transistor for reading or verifying an amount of charge carriers provided for the floating gate 3 during programming. This electric filed effect transistor includes a floating gate 3, a source 6a, a drain 6b, and a channel region formed between the drain and source 6a and 6b.
A control gate 3 of each nonvolatile memory cell is connected to an adjacent word line 10, the source 6a of the nonvolatile memory cell is commonly connected to the bit line 13 adjacent to the drain of a nonvolatile memory cell. The selection transistors 12 are connected to the bit line 13, and a metal contact hole 8 per 32 nonvolatile memory cells or more is connected to the selection transistor 12 in a column direction. Hence, an effective cell size can be reduced.
However, a size of a unit cell increases because of the selection transistors. Furthermore, a program operation by tunneling, which is an operation with low power consumption, is not possible, because two cells adjacent in a direction of word lines 10 are under the same bias condition.
FIG. 2C illustrates an alternative to FIG. 2A of an array of memory cells having a simple stacked-gate structure. A plurality of metal bit lines 9 are formed, spaced apart from one another by a predetermined distance in a column direction and each bit line is completely divided into a source line 15 and a drain line 14 in the same direction as the metal bit lines 9.
The source 6a shown in FIG. 1B is connected to the source line 15 and the drain 6b of a nonvolatile memory cell is connected to the drain line 14. One metal contact hole 8 is connected to each metal bit line 9, and the control gates 5 are connected to a plurality of word lines 10. However, in this arrangement, the size of a unit cell increases because of the division of bit lines.
FIG. 3 is a cross-sectional view showing a structure of a nonvolatile memory device having split channel cells. As shown in FIG. 3, a floating gate 3 is formed on the oxide layer 2 formed on a p-type semiconductor substrate 1. A control gate 5 is formed over the floating gate 3. An insulating layer 16 is formed on the entire surface and a selection gate 17 is formed on the entire surface including the control gate 5 and the floating gate 3. A dielectric film 4 is formed between the control gate 5 and the floating gate 3. A source 6a is formed beneath the surface of the semiconductor substrate 1 to be set off from the floating gate 3, and a drain 6b is formed beneath the surface of the semiconductor substrate 1 at the other side of the floating gate 3.
FIG. 4A is a cross-sectional view of a nonvolatile memory device having split channel cells and FIG. 4B is a cross-sectional view of the nonvolatile memory device in a direction of channel width shown in FIG. 4A.
As shown in FIG. 4A, floating gates 3 are formed over a p-type semiconductor substrate 1, spaced apart from one another by a predetermined distance and a control gate 5 is formed over the floating gate 3. A tunneling oxide layer 2 is formed between the floating gate 3 and the semiconductor substrate 1, and a dielectric film 4 is formed between the floating gate 3 and the control gate 5. A source 6a is formed beneath the surface of the semiconductor substrate 1 to be offset from the floating gate 3 and a drain 6b is formed beneath the surface of the semiconductor substrate 1 at the other side of the floating gate 3.
As shown in FIG. 4B, the field oxide layers 18, spaced apart from one another by a predetermined distance, are formed on the surface of the semiconductor substrate 1 for insulating one cell from another. Gate insulating layers 19 are formed on the semiconductor substrate 1 between the field oxide layers 18. Floating gates 3 are formed to partially overlap the field oxide layers 18. The dielectric film 4 is formed on a predetermined area of the floating gate 3, and the control gates 5 are formed on the dielectric film 4. Cap insulating layers 20 are formed on the control gate 5 and sidewall spacers 21 are formed on both sides of the cap insulating layers 20 and the control gate 5, erases gates 17 are formed on the cap insulating layers 20 and on the field oxide layer 18. The tunneling oxide layers 22 are formed at interface of the floating gate 3 and the erase gate 17.
However, related nonvolatile memory devices have various problems. For example, though the array having a simple stacked-gate structure of FIG. 2C provides a minimum effective cell size, a program disturb is still generated.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.